1. Field of the Invention
The present invention relates to data transfer systems and, in particular, to a synchronization circuit having a finite metastable state for minimizing errors in asynchronous data transfer.
2. Discussion of the Prior Art
Computer systems are subject to significant rates of system failure that result from unreliable interactions between asynchronous subsystems. For example, when communication occurs between two subsystems, it is virtually impossible to eliminate signals that are not logically defined. These signals are often referred to as "runt" or "split" pulses.
As shown in FIG. 1, in conventional digital systems, the incoming data signal to a receiving logic circuit is typically first provided to a synchronizer circuit which usually consists of a D or RS flip-flop. The synchronizer circuit, which is driven at the clock frequency of the receiving logic circuit, converts the asynchronous incoming signal to a signal which is synchronous with the receiving circuit.
It is well known that there exists a trigger pulse that causes a conventional flip-flop to go into a metastable region. For example, referring to FIGS. 1 and 2, the synchronizer circuit shown in FIG. 1 will latch an asynchronous data signal arriving at the input pad of a digital logic circuit at whatever the data level is at the clock sampling time. Since the data signal can change at any time relative to the clock sampling frequency, the synchronizer output can provide a "quasi" level signal which is somewhere between 0 and 1. This quasi level signal will result in violation of the logic function of the digital circuit, causing the associated system to crash.
This "metastable" value between logic levels 0 and 1 is indeterminate in the time domain. Therefore, although it will resolve itself over time, there is no fixed time interval sufficiently long to insure that the flip-flop, with probability 1, will reach a defined output state.
The above-described metastable condition is discussed in greater detail by Chaney et al, "Beware The Synchronizer", Compcon 72, 1972, pp. 317-319.
Techniques for measuring the time required for the flip-flop output to settle out, i.e., to reach one of the two stable states, are described by Pechoucek, "Anomalous Response Times of Input Synchronizers", IEEE Transactions on Computers, February 1976, pp. 133-139 and by Rosenberger et al, "Flip-flop Resolving Time Test Circuit", IEEE Journal of Solid-State Circuits, Vol. SC-17, No. 4, August 1982, pp. 731-738.
Examples of approaches taken toward a solution to the above-described problem are provided by U.S. Pat. Nos. 4,093,878 issued to Paschal et al on June 6, 1978; 4,398,105 issued to Keller on Aug. 9, 1983; and 4,529,892 issued to Reilly et al on July 6, 1985.
However, none of the above-identified patents discloses a simple, two-stage synchronizer design which relies upon the mutual exclusiveness of the potential metastable solutions of two stages to resolve the metastable state of the synchronizer.